European Transactions on Telecommunications Focus on Synchronization of Digital Networks

Papers featured

"Characterization of Timing Signal and Clocks",
(invited paper),
D. De Seta, M. Carbonelli, D. Perucchini.

"Mutual Clock Synchronization in Global Digital Communication Networks",
W. C. Lindsey, J. H. Chen.

"Design Aspects and Analysis of SDH Equipment Clocks",
R. Urbansky, W. Sturm.

"Effects of Fixed Frequency Clock Offsets in Synchronous Digital Hierarchy Networks",
P. E. Sholander, C. B. Autry, H. L. Owen.

"Stability Requirements of Oscillators Used for Synchronization Loops in Communications Systems",
A. Welti, U. Bernhard.

Abstracts of the papers

Characterization of Timing Signal and Clocks

The characteristics of timing signals at the output of autonomous and slave clocks are thoroughly investigated: first, a mathematical model of timing signals is introduced, then models for describing autonomous and slave clocks are presented whereby an analysis of their behaviour in a synchronization network is carried out. Further, two commonly used measurement configurations are described in order to identify the measurement set-ups more useful for telecommunication applications; the most frequently used quantities for characterizing time and frequency stability are introduced and deeply investigated. Finally, the stability quantities behaviour both for autonomous and slave clocks is studied, with the aim at providing synchronization network designers with powerful tools for network planning and for assessing network performance.

Mutual Clock Synchronization in Global Digital Communication Networks

There are numerous synchronization methodologies available for consideration in solving the problem of network synchronization in digital communication networks. They include: independent clocks, pulse stuffing, elastic stores, master-slave hierarchical, time reference distribution, mutual synchronization, etc. This paper considers the network synchronization performance achievable using the method of mutual clock synchronization observed first by Christiaan Huygens in 1665. Network synchronization performance metrics studied include: nodal timing accuracy, timing jitter, slip rate, time interval between slips, probability of loss of synchronization. These metrics are shown to depend upon the distance (range) between clocks, ranging error, clock stability, nodal phase error processing bandwidth, data rate, signal-to-noise ratio and network connectivity. In this regard, the mutual synchronization performance achievable with long wavelength biological rhythms and electric power system rhythms is compared with the performance achievable using short wavelength rhythms required in wideband and broadband digital communications networks. The results are further applied to the problem of synchronizing a satellite communications network. When intrasatellite communication crosslinks (links between satellites in the same orbital plane) are used in a constellation of communication satellites, it is shown that the maximum data rate, the network connectivity and the constellation altitude drive the achievable network synchronization performance; the latter is set by technological limitations due to clock frequency stability, the maximum range between satellites and the minimum ranging error achievable by the ranging system. In this sense, low Earth orbits (LEO) are preferred over geosynchronous (GEO)Earth orbits. The theory is also applied to theTeledesic and Iridium networks.

Design Aspects and Analysis of SDH Equipment Clocks

Network synchronization has gained increasing attention since the introduction of the Synchronous Digital Hierarchy (SDH). The network synchronization performance and the SDH-internal bit rate adaptation technique have a major impact on the phase transfer characteristics of SDH-based networks. Excessive jitter or wander may result in bit errors or frame slips within digital exchanges. This paper will discuss the requirements with respect to SDH Equipment Clocks (SEC), which are the basis for improved network synchronization. Two parameters have a significant impact on the phase error generated by the clock: the oscillator performance and the phase detector characteristic. This paper proposes a synthesizer-based PLL structure employing a fixed frequency highly stable oscillator. A novel approach for an all-digital phase detector provides enhanced resolution, thereby reducing the phase error. Analytical and simulation results demonstrate the feasibility of this approach, which can be extended to a broader application range.

Effects of Fixed Frequency Clock Offsets in Synchronous Digital Hierarchy Networks

SDH networks require synchronous clocking in order to minimize network wander and jitter. In practice, the clocks in SDH networks are not ideal and thus are not all perfectly synchronous. The operation of SDH networks with non-ideal clocks results in undesirable wander and jitter effects. Two different philosophies are being used to minimize these undesirable synchronization effects in SDH networks. In Europe, where it is difficult to tighten clock specifications due to the multinational synchronization environment, desynchronizer designs are made more robust. In North America, where Synchronous Optical Network (SONET) is used, the specifications of both the clocks and the synchronization distribution are being tightened. Even with these different approaches, non-ideal synchronization effects still exist in SDH networks. In particular, the STM-N, AU, and TU overhead bytes cause gapped pointer effects when traditional fixed threshold pointer processors are used. Another type of pointer processor, a uniform pointer processor, can remove the gapped pointer effects caused by the STM-N, AU, and TU overhead bytes. Additionally, a compensating desynchronizer may be used to remove the gapped effects caused by the VC overhead bytes. If these gapped effects are not removed, then they cause jitter and wander in a reconstructed PDH signal. This paper focuses on the case where the SDH network clocks have fixed frequency offsets. An E1-rate (2048 kb/s) payload, which is transported over a network consisting of SDH and PDH islands, is used to show the effects of this non-ideal clocking in SDH networks. In theory, clock frequency differences in SDH networks are accommodated by the pointer processor mechanism without slips (i.e. losing or repeating data). In practice, non-ideal synchronization may still cause slips.

Stability Requirements of Oscillators Used for Synchronization Loops in Communications Systems

An imperfect clock timing recovery in receivers of modern communication systems degrades the performance of synchronization loops and, hence, the overall system reliability and data transmission quality. In this paper, the phase-locked loop (PLL) for the carrier recovery and the delay-locked loop (DLL) for the clock timing recovery of the pseudonoise (PN) code in direct-sequence spread-spectrum systems are analyzed regarding the impacts of imperfect oscillators (including phase noise and a frequency offset between transmitter and receiver) and channel noise on the mean exit time. The optimal design considerations to achieve a maximum mean exit time for second-order synchronization loops can be used to find the required oscillator stability, i.e., the maximum tolerable frequency offset and oscillator phase noise.